Lu Zhang, Ph.D.

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Sr. Silicon Emulation Engineer • Google

October 2019 - Present • Mountain View, California, USA

• Transformed Tensor SoC's emulation build workflow from a manual, fragile process into an automated, reproducible, and scalable pipeline, improving emulation build turnaround by 50%.
• Architected hybrid emulation platforms (CPU models + ZeBu/HAPS) for security, ISP, and TPU, delivering up to 5× speedup in pre-silicon validation and enabling early software bring-up.
• Owned emulation build and deployment methodology for both similation acceleration (SimXL) and silicon validation, ensuring reproducibility and robustness across SoC generations.
• Launched milestone emulation platforms that provided a robust baseline for the emulation team to extend features and diversify SoC configurations throughout pre-silicon development.
• Integrated MIPI CSI transactors and developed drivers — the first-of-its-kind in Google's emulation environment — enabling emulated camera streams and expanding ISP validation coverage.
• Validated high-impact IPs (CPU cache, ISP, TPU) across emulation and silicon, ensuring system-level functionality and performance.
• Partnered cross-functionally with silicon design, DV, infrastructure, and software teams to streamline emulation model deployment, bring-up, regression, and validation cycles.
• Collaborated with emulation vendors — primarily Synopsys, with exposure to Cadence and Siemens — to drive tool feature development and resolve critical field issues.
• Pioneering integration of GenAI tooling into emulation workflows for log triage, testbench support, and AI-driven iteration.

Ph.D. Researcher • University of California - San Diego

September 2012 - October 2019 • La Jolla, California, USA

• Built LLVM extensions for persistent memory debugging (GitHub: LLVM-NVX and NvxBench).
• Published in top architecture and systems research venues: ATC, SOSP, ASPLOS, and FPGA.

Earlier Career • IMEC and Intel

August 2009 - August 2012 • Belgium and The Netherlands

• Intel: Developed matrix/image accelerators for mobile SoCs.
• IMEC: Developed a hardware accelerator for CNN-like stereo matching.

Ph.D. in Computer Science and Engineering

University of California - San Diego • La Jolla, California, USA

M.S. in Embedded Systems

Delft University of Technology • Delft, The Netherlands

B.Eng. in Electrical Engineering

Shandong University • Ji'nan, Shandong, China

Pangolin: A Fault‑Tolerant Persistent Memory Programming Library

Lu Zhang and Steven Swanson

2019 USENIX Annual Technical Conference (ATC) • 2019

DOI: 10.5555/3358807.3358884

Basic Performance Measurements of the Intel Optane DC Persistent Memory Module

Joseph Izraelevitz, Jian Yang, Lu Zhang, Juno Kim, Xiao Liu, Amirsaman Memaripour, Yun Joon Soh,

Zixuan Wang, Yi Xu, Subramanya R. Dulloor, Jishen Zhao, and Steven Swanson

arXiv: Distributed, Parallel, and Cluster Computing • 2019

DOI: 10.48550/arXiv.1903.05714

NOVA‑Fortis: A Fault‑Tolerant Non‑Volatile Main Memory File System

Jian Xu, Lu Zhang, Amirsaman Memaripour, Akshatha Gangadharaiah, Amit Borase, Tamires Da Silva,

Andy Rudoff, and Steven Swanson

ACM Symposium on Operating Systems Principles (SOSP) • 2017

DOI: 10.1145/3132747.3132761

Moonwalk: NRE Optimization in ASIC Clouds

Moein Khazraee, Lu Zhang, Luis Vega, and Michael Taylor

ACM Intl. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) • 2017

DOI: 10.1145/3037697.3037749

Power Side Channels in Security ICs: Hardware Countermeasures

Lu Zhang, Luis Vega, and Michael Taylor

arXiv: Cryptography and Security • 2019

DOI: 10.48550/arXiv.1605.00681

Real‑time High‑Definition Stereo Matching on FPGA

Lu Zhang, Ke Zhang, Tian Sheuan Chang, Gauthier Lafruit, Georgi Kuzmanov, and Diederik Verkest

ACM Symposium on Field Programmable Gate Arrays (FPGA) • 2011

DOI: 10.1145/1950413.1950428