Lu Zhang, Ph.D.

Sr. Silicon Engineer • Google • Mountain View, CA, USA

Experienced silicon design and emulation engineer with expertise in HW/SW co-design, building reliable SoC emulation platforms, developing and integrating emulation IPs and transactors, and validating SoC functionality and performance across emulation and silicon. Proficient in Verilog/SystemVerilog, C/C++, Bash, Python, and Linux kernel development. Delivered robust, feature-rich ZeBu models for pre-silicon validation and early software development across multiple generations of Google Tensor SoCs.

Skills

Hardware Design: RTL • SystemVerilog • Tcl • Waveform Analysis • HW/SW Co-Design
Software/Programming: Python • C/C++ • DPI-C • Bash • LLVM • Linux Kernel
Domain Expertise: SoC • ARM • ZeBu • Emulation IP • Hybrid Emulation • Silicon Validation

Work Experience

Sr. Silicon Engineer • Google

October 2019 - Present • Mountain View, California, USA

[Ownership] Owned SoC emulation build and deployment (methodology and deliverables) for pre-silicon validation, ensuring silicon-accurate validation and early software development across multiple SoC generations.
[Teamwork] Designed a robust and flexible emulation testbench, supporting the emulation team to extend features, improve debuggability, and diversify emulation configurations.
[Innovation] Developed and integrated multiple emulation IPs for simplifying software development and improving debugging capabilities — including clock meters, teleporting UART, and bus traffic monitors — the first-of-its-kind in Google's pre-silicon environment.
[Architecture] Architected hybrid emulation platforms (ARM Fast Models + IP emulation) for security, ISP, and TPU, delivering up to 5× speedup in pre-silicon execution and enabling early software bring-up.
[DevOps] Transformed Tensor SoC's emulation build workflow from a manual, fragile process into an automated, reproducible, and scalable pipeline, improved emulation build turnaround by 50%.
[Validation] Validated high-impact IPs (CPU cache, ISP, TPU) across emulation and silicon, ensuring system-level functionality and performance.
[Collaboration] Partnered cross-functionally with silicon design, DV, infrastructure, and software teams to streamline emulation model deployment, bring-up, regression, and validation cycles.
[Vendor Relations] Collaborated with emulation vendors — primarily Synopsys, with exposure to Cadence and Siemens — to drive tool feature development and resolve critical field issues.

Ph.D. Researcher • University of California - San Diego

September 2012 - October 2019 • La Jolla, California, USA

[LLVM] Built PmemSanitizer for debugging persistent memory (pmem) applications (Source: GitHub, Fixed Bugs: PMDK)
[C++] Developed application libraries for fail-safe pmem programming (Publication: ATC'2019).
[Python] Modeled engineering costs across technology nodes to optimize ASIC deployment in cloud services (Publication: ASPLOS'2017).
[Research] Published in top architecture and systems research venues: ATC, SOSP, and ASPLOS.

Earlier Career • IMEC and Intel

August 2009 - August 2012 • Belgium and The Netherlands

[Intel] Developed matrix-compute accelerators for image processing.
[IMEC] Developed a hardware accelerator for CNN-like stereo matching (Publication: FPGA'2011).